//this is a module that used to divide data
//Last modified by yangjao at 2021/5/10

module Divide(
    input wire clk,
    input wire rst_n,
    input wire W_reg_en,
    input wire reset,
    input wire[1:0] S,
    input wire[31:0] W,
    input wire[31:0] W_j_7_add_W_j_16,

    output wire[31:0] W_i,
    output wire[31:0] W_i_4,
    output wire[31:0] W_j_7,
    output wire[31:0] W_j_16
);

wire[31:0] W0_data_in, W0_data_out;
wire[31:0] W1_data_out;
wire[31:0] W2_data_out;
wire[31:0] W3_data_out;
wire[31:0] W4_data_out;
wire[31:0] W5_data_out;
wire[31:0] W6_data_out;
wire[31:0] W7_data_out;
wire[31:0] W8_data_out;
wire[31:0] W9_data_out;
wire[31:0] W10_data_out;
wire[31:0] W11_data_out;
wire[31:0] W12_data_out;
wire[31:0] W13_data_out;
wire[31:0] W14_data_out;
wire[31:0] W15_data_out;
wire[31:0] W16_data_out;
wire[31:0] W17_data_out;
wire[31:0] W18_data_out;
wire[31:0] W19_data_out;

wire[31:0] SHA256_W, SM3_W;

Registers1 W0(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W0_data_in),

    .data_out(W0_data_out)
);

Registers1 W1(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W0_data_out),

    .data_out(W1_data_out)
);

Registers1 W2(
    .clk(clk),
    .rst_n(rst),
    .reg_en(W_reg_en),
    .data_in(W1_data_out),

    .data_out(W2_data_out)
);

Registers1 W3(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W2_data_out),

    .data_out(W3_data_out)
);

Registers1 W4(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W3_data_out),

    .data_out(W4_data_out)
);

Registers1 W5(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W4_data_out),

    .data_out(W5_data_out)
);

Registers1 W6(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W5_data_out),

    .data_out(W6_data_out)
);

Registers1 W7(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W6_data_out),

    .data_out(W7_data_out)
);

Registers1 W8(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W7_data_out),

    .data_out(W8_data_out)
);

Registers1 W9(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W8_data_out),

    .data_out(W9_data_out)
);

Registers1 W10(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W9_data_out),

    .data_out(W10_data_out)
);

Registers1 W11(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W10_data_out),

    .data_out(W11_data_out)
);

Registers1 W12(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W11_data_out),

    .data_out(W12_data_out)
);

Registers1 W13(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W12_data_out),

    .data_out(W13_data_out)
);

Registers1 W14(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W13_data_out),

    .data_out(W14_data_out)
);

Registers1 W15(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W14_data_out),

    .data_out(W15_data_out)
);

Registers1 W16(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W15_data_out),
    
    .data_out(W16_data_out)
);

Registers1 W17(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W16_data_out),

    .data_out(W17_data_out)
);

Registers1 W18(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W17_data_out),

    .data_out(W18_data_out)
);

Registers1 W19(
    .clk(clk),
    .rst_n(rst_n),
    .reg_en(W_reg_en),
    .data_in(W18_data_out),

    .data_out(W19_data_out)
);

//S==00,output=in1 S==01,output=in2 S==11,output=in3 default,output=in1
MUX_3_1 MUX1(
    .S(S),
    .data_in1(W),
    .data_in2(SHA256_W),
    .data_in3(SM3_W),

    .data_out(W0_data_in)
);

W_out W_out1(
    .select(S[1]),
    .data_in1(W0_data_out),
    .data_in2(W4_data_out),
    .data_in3(W6_data_out),
    .data_in4(W15_data_out),

    .W_i(W_i),
    .W_i_4(W_i_4),
    .W_j_7(W_j_7),
    .W_j_16(W_j_16)
);

endmodule